1. Technical Field
The present invention relates generally to a semiconductor circuit, and more particularly, to controlling latency in a semiconductor device.
2. Related Art
A CAS latency (CL) in a data read operation generally refers to the number of clock cycles counted from the input of the read command to the output of the first data. That is, the CAS latency (CL) is a time interval from the input of a read command, which is synchronized with an external clock signal, to the output of the first data through a DQ pin.
In addition, there is a delay time associated with a data output path in a semiconductor circuit, which should also be taken into consideration.
The delay characteristics of a replica delay for compensating the delay time in a data output path may be changed, depending on the power supply voltage variations.
Therefore, the latency associated with a delay time in a data output path as well as the CAS latency should be addressed in a semiconductor circuit.